Modeling of Jitter in Bang-Bang Clock and Data Recovery Circuits

Clock and data recovery (CDR) circuits incorporating bangbang (binary) phase detectors (PDs) have recently found wide usage. In contrast to their linear counterparts, bang-bang PDs relax the speed and precision required of flipflops and other circuits in the signal path, reducing the complexity and the power dissipation. However, the heavily nonlinear nature of these PDs makes the loop analysis difficult. This paper describes an approach to modeling bang-bang CDR loops with emphasis on jitter characteristics. The methodology predicts jitter transfer, tolerance, and generation as well as the bit error rate (BER). A 1-Gb/s CMOS CDR circuit is designed and fabricated as an experimental vehicle to validate the predictions. The next section of the paper develops the basic model to be used in the analysis of the loop. Section III applies the model to jitter characteristics and BER. Section IV determines the capture range and Section V presents the experimental results.